- Design Verification Engineer 2-3K·13薪
- Sys Test/Validation Engineer 15-23K·13薪
- 人工智能计算平台软件开发工程师 30-55K·13薪
- 项目经理/主管 45-55K·13薪
- 高级AI编译器工程师 25-50K
- 高级AI软件开发工程师 25-50K
- 高级模型优化算法工程师 25-50K
- Firmware Development Engineer固件开发 3-4K·13薪
- 编译器研发架构师 40-70K
- 大模型llm算法实习生 300-350元/天
- 算法实习生 - 模型剪枝/量化(可远程) 300-350元/天
- 图形驱动开发实习生Graphics Driver Intern 200-350元/天
- C/C++系统设计实习生 System Design Intern 200-350元/天
- BIOS 验证实习生(BIOS QA Intern) 200-350元/天
- 可测试性设计实习生(DFT Design Intern) 300-350元/天
职位描述:
- C++
- Verilog
- Perl
- IC验证
- FPGA开发
- 电路设计
薪资面谈,工作地:上海or北京 THE ROLE: AMD S3 team is the Semi-Customized Unit. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with front-end and IP team to verify the chip pervasive logic and low power management logic. THE PERSON: Has related knowledge for design verification and good debug skills. Has good communication skills and be able to work both independently and in a team. KEY RESPONSIBILITIES: • Develop test plan according to the specification and review with Architect and SOC/IP designer. • Develop test scenarios to verify the design and analyze the coverage • Complete the verification task before TO. PREFERRED EXPERIENCE: • Proficient in one kind of simulation tool like VCS, have good debug skill. • Familiar with SystemVerilog/C/C++ language. • Have the knowledge for UVM. • Familiar with script language like SHELL/Perl/Python. • Have experience for SOC Clock, Reset verification. • Have experience for low power management verification. • Familiar with UPF and have experience for NLP simulation. • Good written and spoken English ACADEMIC CREDENTIALS: • Bachelor or Master, major in EE, CS or related area + 8 years working experience LOCATION: Shanghai
蔡女士 2周内活跃
北京海淀区超威半导体技术开发(北京)有限公司科学院南路2号