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Design Verification Engineer 2-3K·13薪

职位描述:

  • C++
  • Verilog
  • Perl
  • IC验证
  • FPGA开发
  • 电路设计

薪资面谈,工作地:上海or北京 THE ROLE: AMD S3 team is the Semi-Customized Unit. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with front-end and IP team to verify the chip pervasive logic and low power management logic. THE PERSON: Has related knowledge for design verification and good debug skills. Has good communication skills and be able to work both independently and in a team. KEY RESPONSIBILITIES: • Develop test plan according to the specification and review with Architect and SOC/IP designer. • Develop test scenarios to verify the design and analyze the coverage • Complete the verification task before TO. PREFERRED EXPERIENCE: • Proficient in one kind of simulation tool like VCS, have good debug skill. • Familiar with SystemVerilog/C/C++ language. • Have the knowledge for UVM. • Familiar with script language like SHELL/Perl/Python. • Have experience for SOC Clock, Reset verification. • Have experience for low power management verification. • Familiar with UPF and have experience for NLP simulation. • Good written and spoken English ACADEMIC CREDENTIALS: • Bachelor or Master, major in EE, CS or related area + 8 years working experience LOCATION: Shanghai

蔡女士

蔡女士 2周内活跃

超威半导体 · 招聘HR
工作地址:

北京海淀区超威半导体技术开发(北京)有限公司科学院南路2号

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更新时间:2024-05-18