- Verification Application Engineer 30-50K·13薪
- HAPS Application Engineer (FPGA) 30-50K·13薪
职位描述:
- C++
- IC验证
- Synopsys
- Verilog
- 电路设计
- 电子半导体
The verification AE works with Synopsys Sales Team on product demonstrations, evaluations, and competitive benchmarking. He/She plays an active role in account planning and works as part of the account team to develop solutions to customer problems based on their insight into the customers' needs and issues. He/She is the face of Synopsys at the customer site and the eyes and ears for Synopsys at this account. Requirements: BS degree in CS/EE with 3+ years of experience as a verification engineer. Experience in developing verification environments for complex ASICs using SystemVerilog or SystemC/C++ is required Experience with verification methodologies such as UVM is preferable Understanding of standard bus protocols such as AMBA, USB and PCI-E or other leading protocols is a plus Excellent verbal and written communication skills Excellent customer interface, negotiation, communication and planning skills
常先生 3日内活跃
北京海淀区融科资讯中心A座711